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mos integrated circuit data sheet m m m m m pd78042f, 78043f, 78044f, 78045f the m pd78042f, m pD78043F, m pd78044f, and m pd78045f are 8-bit single-chip microcomputers that incorpo- rate many hardware peripherals such as an fip ? controller/driver, 8-bit resolution a/d converter, timer, serial interface, and interrupt controller. the one-time prom and eprom models that can operate in the same voltage range as that of masked rom models, and various development tools are provided. the functions of these microcomputers are described in detail in the following users manual. be sure to read this manual when you design a system using any of these microcomputers. m m m m m pd78044f sub-series users manual : u10908e 78k/0 series user's manual, instruction: ieu-1372 features ? high-capacity rom and ram 1990 item program memory data memory product name (rom) internal high-speed ram buffer ram fip display ram m pd78042f 16k bytes 512 bytes 64 bytes 48 bytes m pD78043F 24k bytes m pd78044f 32k bytes 1024 bytes m pd78045f 40k bytes ? wide range of instruction execution time - from ? 8-bit resolution a/d converter: 8 channels high-speed (0.4 m s) to ultra low-speed (122 m s) ? serial interface: 2 channels ? i/o ports: 68 ? timer: 6 channels ? fip controller/driver: total display outputs: 34 ? power supply voltage: v dd = 2.7 to 5.5 v applications cd players, cassete tape recorders, tuners, minicomponent stereos, vcrs, microwave ovens, ecrs, etc. ordering information part number package m pd78042fgf- -3b9 80-pin plastic qfp (14 20 mm) m pD78043Fgf- -3b9 80-pin plastic qfp (14 20 mm) m pd78044fgf- -3b9 80-pin plastic qfp (14 20 mm) m pd78045fgf- -3b9 80-pin plastic qfp (14 20 mm) remark indicates rom code number. 8-bit single-chip microcomputer the information in this document is subject to change without notice. the mark h shows major revised points. document no. u10700ej1v0ds00 (1st edition) date published july 1996 p printed in japan h 1996 www.datasheet.net/ datasheet pdf - http://www..co.kr/
2 m pd78042f, 78043f, 78044f, 78045f 78k/0 series product development the 78k/0 series products were developed as shown below. the sub-series names are indicated in frames. h for control for fip driving 100-pin for lcd driving compatible with iebus tm 42/44-pin 64-pin 64-pin 64-pin 64-pin 100-pin 64-pin 80-pin 100-pin 100-pin 80-pin 78k/0 series these products include an uart and can operate at a low voltage (1.8 v). basic subseries for fip driving. total indication output pins: 26 basic subseries for lcd driving. these products include an uart. the y subseries is compatible with the i 2 c bus. products under development products under mass production 80-pin 100-pin pd78018f m pd78014 m pd780001 m pd78002 m pd78018fy m pd78014y m pd78002y m pd78083 m pd780208 m pd78044f m pd78024 m pd78064b m pd78064 m pd78098 m pd78064y m an iebus controller added to the pd78054. m a timer added to the pd78054 and external interface functions enhanced. m an uart and d/a converter added to the pd78014 and i/o function enhanced. m low-voltage (1.8 v) versions of the pd78014. rom and ram variations enhanced. m an a/d converter and 16-bit timer added to the pd78002. m rom-less product of the pd78078 m basic subseries for control an a/d converter added to the pd78002 m the i/o and fip c/d of the pd78044f enhanced. total indication output pins: 53 m a 6-bit u/d counter added to the pd78024. total indication output pins: 34 m counter-measure against emi noise added to the pd78064. m pd78054 m pd78054y m pd78058fy m pd78058f m pd78070a m pd78070ay m pd78078 m pd78078y m counter-measure against emi noise added to the pd78054 m 80-pin pd780308 m pd780308y m sio of the pd78064 enhanced and rom/ram expanded. m 100-pin for lv 100-pin pwm output, lv digital code decoder, built-in hsync counter. pd78p0914 m www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 3 the table below shows the main differences between subseries. function rom timer 8-bit 8-bit serial i/o v dd min. external subseries name capacity 8-bit 16-bit watch wdt a/d d/a interface value expansion for control m pd78078 32k-60k 4ch 1ch 1ch 1ch 8ch 2ch 3ch (uart : 1ch) 88 pins 1.8 v m pd78070a C 61 pins 2.7 v m pd78058f 48k-60k 2ch 69 pins m pd78054 16k-60k 2.0 v m pd78018f 8k-60k C 2ch 53 pins 1.8 v m pd78014 8k-32k 2.7 v m pd780001 8k C C 1ch 39 pins C m pd78002 8k-16k 1ch C 53 pins m pd78083 8k-16k C 8ch 1ch (uart : 1ch) 33 pins 1.8 v C for fip m pd780208 32k-60k 2ch 1ch 1ch 1ch 8ch C 2ch 74 pins 2.7 v C driving m pd78044f 16k-40k 68 pins m pd78024 24k-32k 54 pins for lcd m pd780308 48k-60k 2ch 1ch 1ch 1ch 8ch C 3ch (uart : 1ch) 57 pins 1.8 v C driving m pd78064b 32k 2ch (uart : 1ch) 2.0 v m pd78064 16k-32k compatible m pd78098 32k-60k 2ch 1ch 1ch 1ch 8ch 2ch 3ch (uart : 1ch) 69 pins 2.7 v with iebus for lv m pd78p0914 32k 6ch C C 1ch 8ch C 2ch 54 pins 4.5 v h h h www.datasheet.net/ datasheet pdf - http://www..co.kr/
4 m pd78042f, 78043f, 78044f, 78045f rom internal high-speed ram buffer ram fip display ram internal memory item product name vectored interrupt 16k bytes 512 bytes 64 bytes 48 bytes m pD78043F m pd78042f m pd78044f m pd78045f general registers 8 bits 32 registers (8 bits 8 registers 4 banks) variable instruction execution time for main system clock 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (at 5.0 mhz) for subsystem clock 122 m s (at 32.768 khz) instruction set ? multiplication/division (8 bits 8 bits, 16 bits 8 bits) ? bit (set, reset, test, boolean algebra) i/o ports (including those total : 68 lines multiplexed with fip pins) ? cmos input : 2 lines ? cmos i/o : 27 lines ? n-ch open-drain : 5 lines ? p-ch open-drain i/o : 16 lines ? p-ch open-drain output : 18 lines fip controller/driver total : 34 lines ? segments : 9 to 24 lines ? digits : 2 to 16 lines a/d converter ? 8-bit resolution 8 channels ? power supply voltage: av dd = 4.0 to 5.5 v serial interface ? 3-wire serial i/o/sbi/2-wire serial i/o selectable modes: 1 channel ? 3-wire serial i/o mode (with automatic transmission/ reception function of up to 64 bytes) : 1 channel timer ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel ? 6 bit up/down counter : 1 channel timer output 3 lines (one for 14-bit pwm output) clock output 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz (main system clock: at 5.0 mhz) 32.768 khz (subsystem clock: at 32.768 khz) buzzer output 1.2 khz, 2.4 khz, 4.9 khz (main system clock: at 5.0 mhz) maskable interrupt internal 10 lines, external 4 lines non-maskable interrupt internal 1 line software interrupt 1 line text input internal 1 line power supply voltage v dd = 2.7 to 5.5 v package 80-pin plastic qfp (14 20 mm) instruction cycle functional outline 24k bytes 32k bytes 1024 bytes 40k bytes h h www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 5 contents 1. pin configuration (top view) ........................................................................................ 6 2. block diagram ..................................................................................................................... 8 3. pins functions ..................................................................................................................... 9 3.1 port pins ...................................................................................................................................... 9 3.2 pins other than port pins ................................................................................................... 11 3.3 pin i/o circuits and processing of unused pins ........................................................ 13 4. memory space ...................................................................................................................... 16 5. peripheral hardware functions ............................................................................... 17 5.1 ports ............................................................................................................................................. 17 5.2 clock generator circuit .................................................................................................... 18 5.3 timer/event counter .............................................................................................................. 18 5.4 clock output control circuit ......................................................................................... 21 5.5 buzzer output control circuit ....................................................................................... 21 5.6 a/d converter ........................................................................................................................... 22 5.7 serial interface ...................................................................................................................... 22 5.8 fip controller/driver .......................................................................................................... 24 6. interrupt function and test function .................................................................... 26 6.1 interrupt function ................................................................................................................. 26 6.2 test function ............................................................................................................................ 29 7. standby function ............................................................................................................... 30 8. reset function .................................................................................................................... 30 9. instruction set ................................................................................................................... 31 10. electrical specifications ............................................................................................. 34 11. characteristic curve (reference value) .............................................................. 58 12. package drawing ............................................................................................................... 63 13. recommended soldering conditions ........................................................................ 64 appendix a development tools ......................................................................................... 65 appendix b related documents ......................................................................................... 67 h h h www.datasheet.net/ datasheet pdf - http://www..co.kr/
6 m pd78042f, 78043f, 78044f, 78045f 1. pin configuration (top view) ? 80-pin plastic qfp (14 20 mm) m pd78042fgf- -3b9, m pD78043Fgf- -3b9 m pd78044fgf- -3b9, m pd78045fgf- -3b9 cautions 1. connect the ic (internally connected) pins directly to the v ss . 2. connect the av dd pin to the v dd pin. 3. connect the av ss pin to the v ss pin. p34/ti2 p33/ti1 x1 x2 p37 p36/buz p35/pcl 65 71 70 69 68 67 66 80 79 78 77 76 75 74 73 72 p95/fip7 p112/fip20 p96/fip8 p97/fip9 p113/fip21 p100/fip10 p101/fip11 p102/fip12 p103/fip13 p104/fip14 p105/fip15 v load p106/fip16 p107/fip17 p110/fip18 p111/fip19 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av dd av ref p04/xt1 xt2 v ss 25 40 26 27 28 29 30 31 32 33 34 35 36 37 38 39 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p114/fip22 p71 p115/fip23 p116/fip24 p72 p117/fip25 p120/fip26 p121/fip27 p122/fip28 p123/fip29 p124/fip30 p125/fip31 p126/fip32 p127/fip33 v dd p70 p31/to1 p32/to2 ic p00/intp0/ti0 p01/intp1 p02/intp2 p03/intp3/ci0 p30/to0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p94/fip6 p21/so1 p93/fip5 p92/fip4 p20/si1 p91/fip3 p90/fip2 p81/fip1 p80/fip0 v dd p27/sck0 p26/so0/sb1 p25/si0/sb0 p24/busy p23/stb p22/sck1 p15/ani5 p14/ani4 reset p74 p73 av ss p17/ani7 p16/ani6 www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 7 p00-p04 : port 0 p10-p17 : port 1 p20-p27 : port 2 p30-p37 : port 3 p70-p74 : port 7 p80, p81 : port 8 p90-p97 : port 9 p100-p107 : port 10 p110-p117 : port 11 p120-p127 : port 12 intp0-intp3 : interrupt from peripherals ti0-ti2 : timer input to0-to2 : timer output ci0 : counter input sb0, sb1 : serial bus si0, si1 : serial input so0, so1 : serial output sck0, sck1 : serial clock pcl : programmable clock buz : buzzer clock stb : strobe busy : busy fip0-fip33 : fluorescent indicator panel v load : negative power supply x1, x2 : crystal (main system clock) xt1, xt2 : crystal (subsystem clock) reset : reset ani0-ani7 : analog input av dd : analog power supply av ss : analog ground av ref : analog reference voltage v dd : power supply v ss : ground ic : internally connected www.datasheet.net/ datasheet pdf - http://www..co.kr/
8 m pd78042f, 78043f, 78044f, 78045f 2. block diagram remark the capacities of the internal rom and ram differ depending on the product. to0/p30 ti0/intp0/p00 to1/p31 ti1/p33 to2/p32 ti2/p34 ci0/intp3/p03 si0/sb0/p25 so0/sb1/p26 sck0/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 ani0/p10- ani7/p17 av dd av ss av ref intp0/ti0/p00- intp3/ci0/p03 buz/p36 pcl/p35 16-bit timer/ event counter 8-bit timer/ event counter 1 8-bit timer/ event counter 2 watchdog timer watch timer 6-bit up/down counter serial interface 0 serial interface 1 a/d converter interrupt control buzzer output clock output control v dd v ss ic ram 78k/0 cpu core rom port 0 port 2 port 3 port 7 port 8 port 9 port 10 port 12 fip controller/driver system control p00 p01-p03 p04 p10-p17 p20-p27 p30-p37 p70-p74 p80, p81 p90-p97 p100-p107 p110-p117 p120-p127 fip0-fip33 v load reset x1 x2 xt1/p04 xt2 port 1 port 11 www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 9 3. pins functions 3.1 port pins (1/2) pin name i/o function on reset shared by: p00 input port 0 input only input intp0/ti0 p01 i/o 5-bit i/o port can be specified for input or output in 1-bit input intp1 p02 units. when used as an input port pin, a built-in intp2 p03 pull-up resistor can be used by software. intp3/ci0 p04 note 1 input input only input xt1 p10-p17 i/o port 1 input ani0-ani7 8-bit i/o port can be specified for input or output in 1-bit units. when used as an input port pin, a built-in pull-up resistor can be used by software. note 2 p20 i/o port 2 input si1 p21 8-bit i/o port so1 p22 can be specified for input or output in 1-bit units. sck1 p23 when used as an input port pin, a built-in pull-up resistor can be stb p24 used by software. busy p25 si0/sb0 p26 so0/sb1 p27 sck0 p30 i/o port 3 input to0 p31 8-bit i/o port to1 p32 can be specified for input or output in 1-bit units. to2 p33 can directly drive leds. ti1 p34 when used as an input port pin, a built-in pull-up resistor can be ti2 p35 used by software. pcl p36 a pull-down resistor can be connected in 1-bit units by the mask buz p37 option. notes 1. when the p04/xt1 pins is used as an input port pin, bit 6 (frc) of the processor clock control register (pcc) must be set to 1. at this time, do not use the feedback resistor of the subsystem clock oscillator circuit. 2. when the p10/ani0 through p17/ani7 pins are used as the analog input lines of the a/d converter, be sure to place the port 1 in the input mode. in this case, the built-in pull-up resistors are automatically unused. www.datasheet.net/ datasheet pdf - http://www..co.kr/
10 m pd78042f, 78043f, 78044f, 78045f 3.1 port pins (2/2) pin name i/o function on reset shared by: p70-p74 i/o port 7 input 5-bit n-ch open-drain i/o port can be specified for input or output in 1-bit units. can directly drive leds. a pull-up resistor can be connected in 1-bit units by the mask option. p80, p81 output port 8 output fip0, fip1 2-bit p-ch open-drain high-voltage output port. can directly drive leds. a pull-down resistor can be connected in 1-bit units by the mask option (whether v load or v ss is connected can be specified in bit units). p90-p97 output port 9 output fip2-fip9 8-bit p-ch open-drain high-voltage output port. can directly drive leds. a pull-down resistor can be connected in 1-bit units by the mask option (whether v load or v ss is connected can be specified in 4-bit units). p100-p107 output port 10 output fip10-fip17 8-bit p-ch open-drain high-voltage output port. can directly drive leds. a pull-down resistor can be connected in 1-bit units by the mask option (whether v load or v ss is connected can be specified in 4-bit units). p110-p117 i/o port 11 input fip18-fip25 8-bit p-ch open-drain high-voltage i/o port. can be specified for input or output in 1-bit units. can directly drive leds. a pull-down resistor can be connected in 1-bit units by the mask option (whether v load or v ss is connected can be specified in 4-bit units). p120-p127 i/o port 12 input fip26-fip33 8-bit p-ch open-drain high-voltage i/o port can be specified for input or output in 1-bit units. can directly drive leds. a pull-down resistor can be connected in 1-bit units by the mask option (whether v load or v ss is connected can be specified in 4-bit units). www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 11 3.2 pins other than port pins (1/2) pin name i/o function on reset shared by: intp0 input valid edge (rising, falling, or both rising and falling edges) can input p00/ti0 intp1 be specified. p01 intp2 external interrupt input p02 intp3 falling edge-active external interrupt input input p03/ci0 si0 input serial data input lines of serial interface input p25/sb0 si1 p20 so0 output serial data output lines of serial interface input p26/sb1 so1 p21 sb0 i/o serial data i/o lines of serial interface input p25/si0 sb1 p26/so0 sck0 i/o serial clock i/o lines of serial interface input p27 sck1 p22 stb output automatic transmission/reception strobe output line of serial input p23 interface busy input automatic transmission/reception busy input line of serial interface input p24 ti0 input external count clock input to 16-bit timer (tm0) input p00/intp0 ti1 external count clock input to 8-bit timer (tm1) p33 ti2 external count clock input to 8-bit timer (tm2) p34 to0 output 16-bit timer output (multiplexed with 14-bit pwm output) input p30 to1 8-bit timer output p31 to2 p32 ci0 input clock input to 6-bit up/down counter input p03/intp3 pcl output clock output (for trimming main system clock and subsystem input p35 clock) buz output buzzer output input p36 fip0, fip1 output high-voltage, high-current digit/segment output of fip output p80, p81 fip2-fip9 controller/driver p90-p97 fip10-fip15 output high-voltage, high-current digit/segment output of fip output p100-p105 controller/driver fip16, fip17 output high-voltage segment output of fip controller/driver output p106, p107 fip18-fip25 input p110-p117 fip26-fip33 p120-p127 v load connects pull-down resistor to fip controller/driver www.datasheet.net/ datasheet pdf - http://www..co.kr/
12 m pd78042f, 78043f, 78044f, 78045f pin name i/o function on reset shared by: ani0-ani7 input a/d converter analog input lines input p10-p17 av ref input a/d converter reference voltage input line av dd analog power supply to a/d converter. connected to the v dd pin. av ss a/d converter ground line. connected to the v ss pin. reset input system reset input x1 input connect crystal for main system clock oscillation x2 xt1 input connect crystal for subsystem clock oscillation input p04 xt2 v dd positive power supply v ss ground potential ic internal connection. connected directly to the v ss pin. 3.2 pins other than port pins (2/2) www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 13 3.3 pin i/o circuits and processing of unused pins table 3-1 shows the i/o circuit type of each pin and the processing of unused pins. for the configuration of the i/o circuit of each type, refer to fig. 3-1. table 3-1 i/o circuit type pin name i/o circuit type i/o recommended connections when unused p00/intp0/ti0 2 input connected to v ss . p01/intp1 8-a i/o individually connected to v ss with a resistor. p02/intp2 p03/intp3/ci0 p04/xt1 16 input connected to v dd or v ss . p10/ani0-p17/ani7 11 i/o individually connected to v dd or v ss with a resistor. p20/si1 8-a p21/so1 5-a p22/sck1 8-a p23/stb 5-a p24/busy 8-a p25/si0/sb0 10-a p26/so0/sb1 p27/sck0 p30/to0 5-c p31/to1 p32/to2 p33/ti1 8-b p34/ti2 p35/pcl 5-c p36/buz p37 p70-p74 13-b p80/fip0, p81/fip1 14-a output open p90/fip2-p97/fip9 p100/fip10-p107/fip17 p110/fip18-p117/fip25 15-c i/o individually connected to v dd or v ss with a resistor. p120/fip26-p127/fip33 reset 2 input xt2 16 open av ref connected to v ss . av dd connected to v dd . av ss connected to v ss . v load ic connected directly to v ss . www.datasheet.net/ datasheet pdf - http://www..co.kr/
14 m pd78042f, 78043f, 78044f, 78045f type 8-a type 8-b type 10-a in schmitt trigger input with hysteresis characteristics v dd v dd p-ch p-ch n-ch in/out pull-up enable data output disable input enable type 2 type 5-a type 5-c v dd v dd pull-up enable data output disable p-ch n-ch in/out (mask option) p-ch p-ch n-ch v dd pull-up enable data in/out open-drain output disable v dd p-ch fig. 3-1 pin i/o circuits (1/2) v dd p-ch n-ch p-ch v dd in/out (mask option) pull-up enable data output disable input enable v dd v dd pull-up enable data output disable p-ch in/out n-ch p-ch www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 15 type 11 type 15-c type 16 type 13-b type 14-a v dd v dd data n-ch p-ch p-ch in/out v load (mask option) (mask option) n-ch rd fig. 3-1 pin i/o circuits (2/2) (threshold voltage) v ref pull-up enable data output disable v dd p-ch p-ch n-ch p-ch n-ch input enable v dd + in/out comparator data output disable rd input buffer with intermediate withstand voltage in/out v dd n-ch v dd p-ch (mask option) v dd p-ch p-ch n-ch data out (mask option) (mask option) v dd v load p-ch feedback cut-off xt1 xt2 www.datasheet.net/ datasheet pdf - http://www..co.kr/
16 m pd78042f, 78043f, 78044f, 78045f 4. memory space fig. 4-1 shows the memory map for m pd78042f, m pD78043F, m pd78044f, and m pd78045f. fig. 4-1 memory map note the internal rom and internal high-speed ram capacities vary depending on the product. (see the table below.) product name last address of internal first address of internal rom high-speed ram nnnnh mmmmh m pd78042f 3fffh fd00h m pD78043F 5fffh m pd78044f 7fffh fb00h m pd78045f 9fffh ffffh ff00h feffh fee0h fedfh mmmmh mmmmh ?1 nnnnh + 1 nnnnh 0000h nnnnh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h special function register (sfr) 256 8 bits general register 32 8 bits internal high-speed ram note fip display ram 48 8 bits internal rom note callf entry area program area callt table area inhibited program area vector table area data memory space program memory space inhibited buffer ram 64 8 bits inhibited fb00h faffh fac0h fabfh fa80h fa7fh fa50h fa4fh www.datasheet.net/ datasheet pdf - http://www..co.kr/
17 m pd78042f, 78043f, 78044f, 78045f 5. peripheral hardware functions 5.1 ports i/o ports are classified into the following five types: ? cmos input (p00, p04) : 2 ? cmos input/output (p01 - p03, ports 1 - 3) : 27 ? n-ch open-drain input/output (port 7) : 5 ? p-ch open-drain output (ports 8 - 10) : 18 ? p-ch open-drain input/output (ports 11 and 12) : 16 total : 68 table 5-1 port function product pin function port 0 p00, p04 input-only port p01-p03 i/o port. can be specified for input or output in 1-bit units. when used as input port, internal pull-up resistor can be connected through software. port 1 p10-p17 i/o port. can be specified for input or output in 1-bit units. when used as input port, internal pull-up resistor can be connected through software. port 2 p20-p27 i/o port. can be specified for input or output in 1-bit units. when used as input port, internal pull-up resistor can be connected through software. port 3 p30-p37 i/o port. can be specified for input or output in 1-bit units. when used as input port, internal pull-up resistor can be connected through software. pull-down resistor can be connected in 1-bit units by the mask option. can directly drive led. port 7 p70-p74 n-ch open-drain i/o port. can be specified for input or output in 1-bit units. pull-up resistor can be connected in 1-bit units by the mask option. can directly drive led. port 8 p80, p81 p-ch open-drain output port with high withstand voltage. pull-down resistor can be connected in 2-bit units by the mask option (connection to v load or v ss can be specified in 2-bit units). can directly drive led. port 9 p90-p97 p-ch open-drain output port with high withstand voltage. pull-down resistor can be connected in 1-bit units by the mask option (connection to v load or v ss can be specified in 4-bit units). can directly drive led. port 10 p100-p107 p-ch open-drain output port with high withstand voltage. pull-down resistor can be connected in 1-bit units by the mask option (connection to v load or v ss can be specified in 4-bit units). can directly drive led. port 11 p110-p117 p-ch open-drain i/o port with high withstand voltage. can be specified for input or output in 1-bit units. pull-down resistor can be connected in 1-bit units by the mask option (connection to v load or v ss can be specified in 4-bit units). can directly drive led. port 12 p120-p127 p-ch open-drain i/o port with high withstand voltage. can be specified for input or output in 1-bit units. pull-down resistor can be connected in 1-bit units by the mask option (connection to v load or v ss can be specified in 4-bit units). can directly drive led. www.datasheet.net/ datasheet pdf - http://www..co.kr/
18 m pd78042f, 78043f, 78044f, 78045f 5.2 clock generator circuit the clock generator circuit has two kinds of generator circuits: the main system clock and subsystem clock. the instruction time can be changed. ? 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (with main system clock: 5.0 mhz) ? 122 m s (with subsystem clock: 32.768 khz) fig. 5-1 clock generator circuit block diagram subsystem clock oscillator main system clock oscillator prescaler selector prescaler to intp0 sampling clock standby control circuit cpu clock (f cpu ) clock to hardware peripherals clock output circuit f xt f x xt1/p04 xt2 x1 x2 f x 2 f x 2 2 f x 2 3 f x 2 4 stop f xt 2 2 1 selector noise eliminator selector watch timer f x 8 f x 16 5.3 timer/event counter six channels of timer/event counters are provided. ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel ? 6-bit up/down counter : 1 channel table 5-2 timer/event counter groups and configurations function group 16-bit timer/ 8-bit timer/ watch watchdog 6-bit up/ event counter event counter timer timer down counter interval timer 1 channel 2 channels 1 channel 1 channel external event counter 1 channel 2 channels 1 channel timer output 1 output 2 outputs pwm output 1 output pulse width measurement 1 input square wave output 1 output 2 outputs interrupt request 1 2 1 1 1 test input 1 input www.datasheet.net/ datasheet pdf - http://www..co.kr/
19 m pd78042f, 78043f, 78044f, 78045f internal bus internal bus 8-bit compare register (cr10) 8-bit compare register (cr20) 8-bit timer register 2 (tm2) 8-bit timer register 1 (tm1) output control circuit match match selector selector selector selector selector clear to1/p31 inttm2 to2/p32 inttm1 f x /2 12 f x /2 -f x /2 10 f x /2 -f x /2 10 f x /2 12 ti1/p33 clear ti2/p34 output control circuit internal bus 16-bit compare register (cr00) 16-bit timer register (tm0) 16-bit capture register (cr01) internal bus pwm pulse output control circuit selector 16-bit timer/event counter output control circuit edge detector match selector clear ti0/p00/intp0 f x /2 3 f x /2 2 f x /2 intp0 to0/p30 inttm0 f x fig. 5-2 16-bit timer/event counter block diagram fig. 5-3 8-bit timer/event counter block diagram www.datasheet.net/ datasheet pdf - http://www..co.kr/
20 m pd78042f, 78043f, 78044f, 78045f prescaler 5-bit counter selector selector selector selector f x /2 8 f xt f w f w 2 9 f w 2 8 f w 2 7 f w 2 6 f w 2 5 f w 2 4 f w 2 13 f w 2 14 intwt inttm3 fig. 5-4 watch timer block diagram fig. 5-5 watchdog timer block diagram fig. 5-6 6-bit up/down counter block diagram caution when using the 6-bit up/down counter, set the ci0/p03/intp3 pin in the input mode (set bit 3 of port mode register 0 (pm03) to 1). internal bus 6-bit up/down counter compare register (udcc) 6-bit up/down counter (udc) ci0/p03/intp3 edge detector clear selector load underflow match intp3/intud prescaler selector reset selector control circuit 8-bit counter intwdt maskable interrupt request intwdt nonmaskable interrupt request f x 2 4 f x 2 f wdt 2 f wdt f wdt 2 2 f wdt 2 3 f wdt 2 4 f wdt 2 5 f wdt 2 6 f wdt 2 8 3 www.datasheet.net/ datasheet pdf - http://www..co.kr/
21 m pd78042f, 78043f, 78044f, 78045f 5.4 clock output control circuit clocks of the following frequencies can be output to the clock: ? 19.5 khz/39.1 khz/78.1 khz/156 khz/313 khz/625 khz (with main system clock: 5.0 mhz) ? 32.768 khz (with subsystem clock: 32.768 khz) fig. 5-7 clock output control circuit block diagram 5.5 buzzer output control circuit clocks of the following frequencies can be output to the buzzer: ? 1.2 khz/2.4 khz/4.9 khz (with main system clock: 5.0 mhz) fig. 5-8 buzzer output control circuit block diagram f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f xt selector pcl/p35 sync circuit output control circuit f x /2 10 f x /2 11 f x /2 12 selector output control circuit buz/p36 www.datasheet.net/ datasheet pdf - http://www..co.kr/
22 m pd78042f, 78043f, 78044f, 78045f 5.6 a/d converter an 8-bit resolution 8-channel a/d converter is provided. this a/d converter can be started in the following two modes: ? hardware start ? software start fig. 5-9 a/d converter block diagram 5.7 serial interface two channels of clocked serial interfaces are provided. ? serial interface channel 0 ? serial interface channel 1 table 5-3 serial interface groups and functions function serial interface channel 0 serial interface channel 1 3-wire serial i/o mode ? (msb/lsb first selectable) ? (msb/lsb first selectable) sbi (serial bus interface) mode ? (msb first) 2-wire serial i/o mode ? (msb first) 3-wire serial i/o mode with ? (msb/lsb first selectable) automatic transmission/ reception function ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 intp3/p03 intad intp3 av ss av ref av dd sample & hold circuit voltage comparator successive approximation register (sar) series resistor string falling edge detector control circuit a/d conversion result register (adcr) internal bus tap selector selector www.datasheet.net/ datasheet pdf - http://www..co.kr/
23 m pd78042f, 78043f, 78044f, 78045f fig. 5-11 serial interface channel 1 block diagram internal bus si1/p20 sck1/p22 busy/p24 stb/p23 so1/p21 automatic data trans- mission/reception address pointer (adtp) buffer ram automatic data transmission/ reception interval specification register (adti) serial i/o shift register 1 (sio1) match handshake control circuit 5-bit counter serial clock counter interrupt request signal generator serial clock control circuit selector f x /2 2 -f x /2 9 to2 intcsi1 fig. 5-10 serial interface channel 0 block diagram internal bus serial i/o shift bus release/ command/acknowledge detector serial clock counter serial clock control circuit interrupt request signal generator busy/acknowledge output circuit selector selector selector output latch intcsi0 f x /2 2 -f x /2 9 to2 sck0/p27 so0/sb1/p26 si0/sb0/p25 register 0 (sio0) www.datasheet.net/ datasheet pdf - http://www..co.kr/
24 m pd78042f, 78043f, 78044f, 78045f 5.8 fip controller/driver an fip controller/driver having the following features is provided: (a) automatic output of segment signals (dma operation) and digit signals by automatically reading display data (b) display mode registers (dspm0 and dspm1) that can control an fip of 9 to 24 segments and 2 to 16 digits (c) port pins not used for fip display can be used as output port or i/o port pins. (d) display mode register (dspm1) can adjust luminance in eight steps. (e) hardware suitable for key scan application using segment pins (f) high-voltage output buffer (fip driver) that can directly drive an fip (g) display output pins can be connected to a pull-down resistor by the mask option. fig. 5-12 selecting display modes 9 10 11 12 13 14 15 16 0 17 18 19 20 21 22 23 24 0 2 3 4 5 6 7 8 9 10111213141516 selecting number of digits selecting number of segments caution if the total number of digits and segments exceeds 34, the specified number of digits takes precedence. www.datasheet.net/ datasheet pdf - http://www..co.kr/
25 m pd78042f, 78043f, 78044f, 78045f fig. 5-13 fip controller/driver block diagram internal bus display data memory segment data latch digit signal generator port output latch buffer with high withstand voltage fip0/p80 fip1/p81 fip33/p127 www.datasheet.net/ datasheet pdf - http://www..co.kr/
26 m pd78042f, 78043f, 78044f, 78045f 6. interrupt function and test function 6.1 interrupt function the following three types of interrupt functions are available: ? non-maskable interrupt : 1 ? maskable interrupt : 13 ? software interrupt : 1 table 6-1 interrupt source list note 1 default priority vector table address internal/ external interrupt source name trigger note 2 basic configuration type interrupt type non-maskable intwdt watchdog timer overflow internal 0004h (a) (with watchdog timer mode 1 selected) maskable 0 intwdt watchdog timer overflow (b) (with interval timer mode selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h (d) 3 intp2 000ah 4 intp3 000ch intud 6-bit up/down counter match signal generation internal (b) 5 intcsi0 end of serial interface channel 0 transfer 000eh 6 intcsi1 end of serial interface channel 1 transfer 0010h 7 inttm3 reference time interval signal from watch 0012h timer 8 inttm0 16-bit timer/event counter match signal 0014h generation 9 inttm1 8-bit timer/event counter 1 match signal 0016h generation 10 inttm2 8-bit timer/event counter 2 match signal 0018h generation 11 intad end of a/d converter conversion 001ah 12 intks key scan timing from fip controller/driver 001ch software brk execution of brk instruction 003eh (e) notes 1. default priority is the priority order when several maskable interrupts are generated at the same time. 0 is the highest order and the 12 is the lowest order. 2. basic configuration types (a) to (e) correspond to (a) to (e) in fig. 6-1. www.datasheet.net/ datasheet pdf - http://www..co.kr/
27 m pd78042f, 78043f, 78044f, 78045f fig. 6-1 basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0) internal bus interrupt request priority control circuit vector table address generator standby release signal internal bus interrupt request priority control circuit vector table address generator standby release signal mk ie pr isp if internal bus mk ie pr isp if interrupt request standby release signal priority control circuit vector table address generator sampling clock select register (scs) external interrupt mode register (intm0) sampling clock edge detector www.datasheet.net/ datasheet pdf - http://www..co.kr/
28 m pd78042f, 78043f, 78044f, 78045f fig. 6-1 basic configuration of interrupt function (2/2) (d) external maskable interrupt (except intp0) (e) software interrupt if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specification flag internal bus mk ie pr isp if interrupt request standby release signal priority control circuit vector table address generator external interrupt mode register (intm0) edge detector internal bus priority control circuit vector table address generator interrupt request www.datasheet.net/ datasheet pdf - http://www..co.kr/
29 m pd78042f, 78043f, 78044f, 78045f fig. 6-2 basic configuration of test function 6.2 test function the following test function is available. test input source internal/external name trigger intwt overflow of watch timer internal internal bus mk if test input source (intwt) standby release signal if : test request flag mk : test mask flag www.datasheet.net/ datasheet pdf - http://www..co.kr/
30 m pd78042f, 78043f, 78044f, 78045f 7. standby function the standby function is to reduce the current dissipation of the system and can be effected in the following two modes: ? halt mode : in this mode, the operating clock of the cpu is stopped. by using this mode in combination with the normal operation mode, the system can be operated intermittently, so that the average current dissipation can be reduced. ? stop mode : oscillation of the main system clock is stopped. all the operations on the main system clock are stopped, and therefore, the current dissipation of the system can be minimized with only the subsystem clock oscillating. fig. 7-1 standby function note by stopping the main system clock, the current dissipation can be reduced. when the cpu operates on the subsystem clock, stop the main system clock by setting bit 7 (mcc) of the processor clock control register (pcc). the stop instruction cannot be used. caution when the main system clock is stopped and the subsystem clock is operating, to switch again from the subsystem clock to the main system clock, allow sufficient time for the oscillation to settle before switching, by coding the program accordingly. 8. reset function the system can be reset in the following two modes: ? external reset by reset pin ? internal reset by watchdog timer that detects hang up stop mode (oscillation of main system clock stopped) main system clock operation subsystem clock operation note halt mode (clock supply to cpu stopped. oscillation continues) halt mode note (clock supply to cpu stopped. oscillation continues) stop instruction interrupt request interrupt request css = 0 css = 1 halt instruction interrupt request halt instruction www.datasheet.net/ datasheet pdf - http://www..co.kr/
31 m pd78042f, 78043f, 78044f, 78045f 9. instruction set (1) 8-bit instruction mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz second operand [hl + byte] #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + b] $addr16 1 none first [hl + c] operand a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] mov [hl + b] [hl + c] x mulu c divuw note except for r = a h www.datasheet.net/ datasheet pdf - http://www..co.kr/
32 m pd78042f, 78043f, 78044f, 78045f note (2) 16-bit instruction movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand #word ax rp note sfrp saddrp !addr16 sp none first operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instruction mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none first operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1 www.datasheet.net/ datasheet pdf - http://www..co.kr/
33 m pd78042f, 78043f, 78044f, 78045f (4) call/branch instruction call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand ax !addr16 !addr11 [addr5] $addr16 first operand basic operation br call callf callt br br bc bnc bz bnz compound bt operation bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop www.datasheet.net/ datasheet pdf - http://www..co.kr/
34 m pd78042 f , 78043 f , 78044 f , 78045f 10. electrical specifications absolute maximum rating s ( t a = 25 c) parameter symbol conditions rating unit power supply v dd voltage v load a v dd a v ref a v ss input voltage v i1 p00-p04, p10-p17 (except when used as analog input pins), p20-p27, p30-p37, x1, x2, xt2, reset v i2 p70-p74 n-ch open drain v i3 p110-p117, p120-p127 p-ch open drain output voltage v o1 p01-p03, p10-p17, p20-p27, p30-p37 v o2 p70-p74 v o3 p80, p81, p90-p97, p100-p107, p110-p117, p120-p127 analog input voltage v an ani0-ani7 analog input pin output current, i oh p01-p03, p10-p17, p20-p27, p30-p37 per pin high p01-p03, p10-p17, p20-p27, p30-p37 total p80, p81, p90-p97, p100-p107, p110-p117, p120-p127 per pin p80, p81, p90-p97, p100-p107, p110-p117, p120-p127 total output current, i ol p01-p03, p10-p17, p20-p27, p30-p37, peak value low p70-p74 per pin rms value p70-p74 total pea k value rms value p01-p03, p10-p17, p20-p27, p30-p37 total peak value rms value total power p t note 3 t a = C40 to +60 c dissipation t a = +85 c operating t a ambient temperature storage t stg temperature C0.3 to +7.0 v dd C 40 to v dd + 0.3 C0.3 to v dd + 0.3 C0.3 to v dd + 0.3 C0.3 to +0.3 C0.3 to v dd + 0.3 C0.3 to +16 note 1 v dd C 40 to v dd + 0.3 C0.3 to v dd + 0.3 C0.3 to +16 note 1 v dd C 40 to v dd + 0.3 a v ss C 0.3 to a v ref + 0.3 C10 C30 C30 C120 30 15 note 2 100 60 note 2 50 20 note 2 800 600 C40 to +85 C65 to +150 v v v v v v v v v v v v ma ma ma ma ma ma ma ma ma ma mw mw c c cautio n exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. the parameters apply independently. the device should be operated within the limits specified under dc and ac characteristics. remar k unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin. notes 1 . for pins to which pull-up resistors are connected by the mask option, the rating is C0.3 to v dd + 0.3. 2 . to obtain the rms value, calculate [rms value] = [peak value ] ? duty. h www.datasheet.net/ datasheet pdf - http://www..co.kr/
35 m pd78042f, 78043f, 78044f, 78045f notes 3. permissible total power loss differs depending on the temperature (see the following figure). how to calculate total power loss the following three power consumption are available for the m pd78042f. the sum of the three power consumption should be less than the total power loss p t (80 % or less of ratings is recommended). cpu power consumption: calculate v dd (max.) i dd1 (max.). output pin power consumption: normal output and display output are available. power consumption when maximum current flows into each output pin. pull-down resistor power consumption: power consumption by pull-down resistor connected to display output pin by the mask option. ?0 0 +40 +80 200 400 600 800 temperature [ c] total power loss p t [mw] 1 2 3 www.datasheet.net/ datasheet pdf - http://www..co.kr/
36 m pd78042 f , 78043 f , 78044 f , 78045f the following total power consumption calculation example assumes the case where the characters shown in the figure on the next page are displayed. example : the operating conditions are as follows: v dd = 5 v 10 %, operating at 5.0 mhz supply current ( i d d ) = 21.6 ma display outputs: 11 grid s 10 segments (cut width is 1/16) it is assumed that up to 15 ma flows to each grid pin, and that up to 3 ma flows to each segment pin. it is also assumed that all display outputs are turned off at key scan timings. display output voltage: grid v o 3 = v d d C 2 v (voltage drop of 2 v is assumed.) segment v o 3 = v d d C 0.4 v (voltage drop of 0.4 v is assumed.) voltage applied to fluorescent indication panel ( v loa d ) = C30 v mask-option pull-down resistor = 25 k w the total power loss is calculated by determining power consumptio n 1 t o 3 under the above conditions. 1 power consumption of cpu: 5.5 v 21.6 ma = 118.8 mw 2 power consumption at output pins: total current for all grids grid: ( v dd C v o 3 ) digit width (1 C cut width) = number of grids + 1 15 m a 11 grids 2 v (1 C 1/16) = 25.8 mw 11 grids + 1 total segment current for all dots to be lit segment: ( v dd C v o 3 ) = number of grids + 1 3 m a 31 dots 0.4 v = 3.1 mw 11 grids + 1 3 power consumption at pull-down resistors: grid: ( v o3 C v load ) 2 number of grids digit width = pull-down resistance number of grids + 1 (5.5 v C 2 v C (C30 v)) 2 11 grids (1 C 1/16) = 38.6 mw 2 5 k w 11 grids + 1 segment: ( v o3 C v load ) 2 number of dots to be lit = pull-down resistance number of grids + 1 (5.5 v C 0.4 v C (C30 v)) 2 31 dots = 127.3 mw 2 5 k w 11 grids + 1 total power consumption = 1 + 2 + 3 = 118.8 + 25.8 + 3.1 + 38.6 + 127.3 = 313.6 mw in this example, the total power consumption does not exceed the rated value for the permissible total power loss shown in the graph on the previous page. therefore, the calculation result in this example (313.6 mw) satisfies the requirement. if the total power consumption exceed the rated value for the permissible total power loss, the power consumption must be reduced, by reducing the number of built-in pull-down resistors. www.datasheet.net/ datasheet pdf - http://www..co.kr/
37 m pd78042f, 78043f, 78044f, 78045f 10-segment/11-digit display example t10 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 am i pm j j j f e g d b c a sun mon tue wed thu fri sat 12345 6 78910 0 i s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 abcde f gh i j 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 0 1 1 1 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 fa7ah fa6ah fa79h fa69h fa78h fa68h fa77h fa67h fa76h fa66h fa75h fa65h fa74h fa64h fa73h fa63h fa72h fa62h fa71h fa61h fa70h fa60h display data memory fa6 h fa7 h h www.datasheet.net/ datasheet pdf - http://www..co.kr/
38 m pd78042f, 78043f, 78044f, 78045f main system clock oscillator characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) notes 1. it indicates only the oscillator characteristics. for the instruction execution time, see the ac charac- teristics. 2. time required until oscillation becomes stable after v dd is applied or the stop mode is disabled. cautions 1. if the main system clock oscillator is to be used, wire the area inside the broken line square as follows to avoid influence of wiring capacitance: ? make wiring as short as possible. ? do not cross other signal lines. ? do not get close to lines with fluctuating large current. ? make sure that the connecting points of the capacitor of the oscillator always have the same electric potential as v ss . ? do not connect the oscillator to a ground pattern that conducts a large current. ? do not take out signal from the oscillator. 2. when switching to the main system clock again after the subsystem clock has been used with the main system clock stopped, be sure to set the program to provide enough time for the oscillation to stabilize. resonator recommended circuit parameter conditions min. typ. max. unit ceramic oscillation frequency 1 5 mhz resonator (f x ) note 1 oscillation settling 4 ms time note 2 crystal oscillation frequency 1 4.19 5 mhz (f x ) note 1 oscillation settling v dd = 4.5 to 5.5 v 10 ms time note 2 30 external x1 input frequency 1 5 mhz clock (f x ) note 1 x1 input high, low-level 100 500 ns width (t xh , t xl ) x1 x2 pd74hcu04 m v ss x1 x2 c2 c1 v ss x1 x2 c2 c1 www.datasheet.net/ datasheet pdf - http://www..co.kr/
39 m pd78042f, 78043f, 78044f, 78045f subsystem clock oscillator characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) notes 1. it indicates only the oscillator characteristics. for the instruction execution time, see the ac charac- teristics. 2. time required until oscillation becomes stable after v dd reaching min. of oscillation voltage range. cautions 1. if the subsystem clock oscillator is to be used, wire the area inside the broken line square as follows to avoid influence of wiring capacitance: ? make wiring as short as possible. ? do not cross other signal lines. ? do not get close to lines with fluctuating large current. ? make sure that the connecting points of the capacitor of the oscillator always have the same electric potential as v ss . ? do not connect the oscillator to a ground pattern that conducts a large current. ? do not take out signal from the oscillator. 2. the subsystem clock oscillator is more likely to have malfunctions due to noise than the main system clock oscillator because gain for the subsystem clock oscillator is made lower to reduce current consumption. when using the subsystem clock, be careful about how to connect wires. xt1 xt2 resonator recommended circuit parameter conditions min. typ. max. unit crystal oscillation frequency 32 32.768 35 khz (f xt ) note 1 oscillation settling v dd = 4.5 to 5.5 v 1.2 2 s time note 2 10 external xt1 input frequency 32 100 khz (f xt ) note 1 xt1 input high, low- 5 15 m s level width (t xth , t xtl ) xt1 xt2 c4 c3 v ss r www.datasheet.net/ datasheet pdf - http://www..co.kr/
40 m pd78042 f , 78043 f , 78044 f , 78045f manufacturer product name frequency recommended oscillator voltage range remark (mhz) circuit constant c1 (pf) c2 (pf) min . (v) max. (v) murata mfg. co., ltd. csb1000j 1.00 100 100 2.7 5.5 r d = 4. 7 k w note csa2.00mg040 2.00 100 100 2.7 5.5 cst2.00mg040 2.00 2.7 5.5 built-in capacitor csa4.00mg 4.00 3 0 3 0 2.7 5.5 cst4.00mgw 4.00 2.7 5.5 built-in capacitor csa5.00mg 5.00 3 0 3 0 2.7 5.5 cst5.00mgw 5.00 2.7 5.5 built-in capacitor tdk corp. ccr1000k2 1.00 150 150 2.7 5.5 surface-mount type ccr2.0mc3 2.00 2.7 5.5 built-in capacitor, surface-mount type ccr4.0mc3 4.00 2.7 5.5 built-in capacitor, surface-mount type fcr4.0mc5 4.00 2.7 5.5 built-in capacitor ccr5.0mc3 5.00 2.7 5.5 built-in capacitor, surface-mount type fcr5.0mc5 5.00 2.7 5.5 built-in capacitor matsushita electronics efoec2004a4 2.00 3 3 3 3 2.7 5.5 built-in capacitor components co., ltd. efos2004b5 2.00 3 3 3 3 2.7 5.5 built-in capacitor, surface-mount type efoec3584a4 3.58 3 3 3 3 2.7 5.5 built-in capacitor efos3584b5 3.58 3 3 3 3 2.7 5.5 built-in capacitor, surface-mount type efoec4004a4 4.00 3 3 3 3 2.7 5.5 built-in capacitor efos4004b5 4.00 3 3 3 3 2.7 5.5 built-in capacitor, surface-mount type efoec5004a4 5.00 3 3 3 3 2.7 5.5 built-in capacitor efos5004b5 5.00 3 3 3 3 2.7 5.5 built-in capacitor, surface-mount type recommended oscillator constant m ain system clock: ceramic resonato r (t a = C40 to +85 c) not e when the csb1000j (1.00 mhz) manufactured by murata mfg. is used, a limiting resistor (4.7 k w ) is necessary (see the figure in the next page). when one of other resonators is used, no limiting resistor is required. cautio n the oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. if the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. for this, it is necessary to directly contact the manufacturer of the resonator that being used. www.datasheet.net/ datasheet pdf - http://www..co.kr/
41 m pd78042f, 78043f, 78044f, 78045f recommended sample circuit for the main system clock when the csb1000j manufactured by murata mfg. is used csb1000j v ss v dd x2 x1 rd c2 c1 www.datasheet.net/ datasheet pdf - http://www..co.kr/
42 m pd78042f, 78043f, 78044f, 78045f capacitance (t a = 25 c, v dd = v ss = 0 v) remark unless otherwise specified, the characteristics of the shared pin are the same as the characteristics of the port pin. power supply voltage (t a = C40 to +85 c) notes 1. except for system clock oscillator, display controller/driver, and pwm. 2. operating power supply voltage differs depending on the cycle time. see the ac characteristics . parameter symbol conditions min. typ. max. unit input c in f = 1 mhz unmeasured pins returned to 0 v 15 pf capacitance output c out f = 1 mhz unmeasured pins returned to 0 v 35 pf capacitance input/output c io f = 1 mhz p01-p03, p10-p17, 15 pf capacitance unmeasured pins returned to 0 v p20-p27, p30-p37 p70-p74 20 pf p110-p117, p120-p127 35 pf parameter conditions min. typ. max. unit cpu note 1 2.7 note 2 5.5 v display controller/driver 4.5 5.5 v pwm mode of 16-bit 4.5 5.5 v timer/event counter (tm0) a/d converter 4.0 5.5 v other hardware 2.7 5.5 v www.datasheet.net/ datasheet pdf - http://www..co.kr/
43 m pd78042f, 78043f, 78044f, 78045f conditions high-level input voltage low-level input voltage high-level output voltage low-level output voltage v ih1 v ih2 v ih3 v ih4 v ih5 v ih6 v ih7 v il1 v il2 v il3 v il4 v il5 v il6 v il7 v oh v ol1 v ol2 v ol3 p21, p23 p00-p03, p20, p22, p24-p27, p33, p34, reset p70-p74 n-ch open drain x1, x2 note 2 xt1/p04, xt2 note 2 v dd = 4.5 to 5.5 v p10-p17, p30-p32, p35-p37 v dd = 4.5 to 5.5 v p110-p117, p120-p127 v dd = 4.5 to 5.5 v p21, p23 p00-p03, p20, p22, p24-p27, p33, p34, reset p70-p74 v dd = 4.5 to 5.5 v x1, x2 note 2 xt1/p04, xt2 note 2 v dd = 4.5 to 5.5 v p10-p17, p30-p32, p35-p37 p110-p117, p120-p127 p01-p03, p10-p17, p20-p27, p30-p37, p80, p81, p90-p97, p100-p107, p110-p117, p120-p127 p30-p37, p70-p74 p01-p03, p10-p17, p20-p27 sb0, sb1, sck0 p01-p03, p10-p17, p20-p27, p30-p37, p70-p74 v dd = 4.5 to 5.5 v i oh = C1 ma i oh = C100 m a v dd = 4.5 to 5.5 v, i ol = 15 ma v dd = 4.5 to 5.5 v, i ol = 1.6 ma v dd = 4.5 to 5.5 v, with open-drain and pull-up (r = 1 k w ) i ol = 400 m a parameter symbol max. 0.7v dd 0.8v dd 0.7v dd v dd C 0.5 v dd C 0.5 v dd C 0.3 0.65v dd 0.7v dd 0.7v dd v dd C 0.5 0 0 0 0 0 0 0 0 v dd C 35 v dd C 1.0 v dd C 0.5 v dd v dd 15 note 1 v dd v dd v dd v dd v dd v dd v dd 0.3v dd 0.2v dd 0.3v dd 0.2v dd 0.4 0.4 0.3 0.3v dd 0.3v dd 2.0 0.4 0.2v dd 0.5 v v v v v v v v v v v v v v v v v v v v v v v v v 0.4 unit typ. min. dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) notes 1. pins to which pull-up resistors are connected by the mask option become v dd . 2. if the x1 pin is used for high-level voltage input, the x2 pin is used for low-level voltage input, or vice versa. this is also true for the xt1/p04 pin and xt2 pin. remark unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin. www.datasheet.net/ datasheet pdf - http://www..co.kr/
44 m pd78042 f , 78043 f , 78044 f , 78045f i lih1 i lih2 i lih3 i lih4 i lil1 i lil2 i lil3 i lil4 i loh1 i loh2 i lol1 i lol2 i od r 1 r 2 r 3 r 4 parameter symbol high-level input leakage current low-level input leakage current high-level output leakage current note 4 low-level output leakage current note 4 display output current mask option pull-up resistor software pull- up resistor mask option pull-down resistor conditions unit 3 20 20 3 note 1 3 note 2 C3 C20 C3 note 3 C10 3 20 C3 C10 90 90 500 135 90 150 C15 20 15 20 25 15 40 C25 40 40 65 40 80 typ . min. max. m a m a m a m a m a m a m a m a m a m a m a m a m a ma k w k w k w k w k w k w v in = v dd v in = 15 v p110-p117, p120-p127, v in = v dd v in = 0 v v ou t = v dd v ou t = 15 v v ou t = 0 v v ou t = v loa d = v d d C 35 v v dd = 4.5 to 5.5 v, v o3 = v dd C 2 v v in = 0 v, p70-p74 v in = 0 v, p01-p03, p10-p17, p20-p27, p30-p37 p80, p81, p90-p97, p100-p107, p110-p117, p120-p127 p30-p37, v in = v dd p00-p03, p10-p17, p20-p27, p30-p37, reset x1, x2, xt1/p04, xt2 p70-p74 v dd = 4.5 to 5.5 v p00-p03, p10-p17, p20-p27, p30-p37, reset x1, x2, xt1/p04, xt2 p70-p74 p110-p117, p120-p127 p01-p03, p10-p17, p20-p27, p30-p37, p80, p81, p90-p97, p100-p107, p110-p117, p120-p127 p70-74, n-ch open drain p01-p03, p10-p17, p20-p27, p30-p37, p70-p74 p80, p81, p90-p97, p100-p107, p110-p117, p120-p127 v dd = 4.5 to 5.5 v v o3 C v loa d = 35 v v o3 C v ss = 5 v dc c haracteristic s ( t a = C40 to +85 c, v d d = 2.7 to 5.5 v) notes 1 . when p110 to p117 and p120 to p127 do not contain the pull-down resistors (according to the specification of the mask option), a high-level input leakage current of 150 m a (max.) flows only during 1.5 clocks after a read instruction has been executed to read out port 11 or 12 (p11 or p12) or port mode register 11 or 12 (pm11 or pm12). outside the 1.5 clocks after a read instruction, the current is 3 m a (max.). 2 . when p110 to p117 and p120 to p127 do not contain the pull-down resistors (according to the specification of the mask option), a high-level input leakage current of 90 m a (max.) flows only during 1.5 clocks after a read instruction has been executed to read out p11, p12, pm11, or pm12. outside the 1.5 clocks after a read instruction, the current is 3 m a (max.). 3 . when p70 to p74 do not contain the pull-down resistors (according to the specification of the mask option), a low-level input leakage current of C150 m a (max.) flows only during 1.5 clocks after a read instruction has been executed to read out port 7 (p7) or port mode register 7 (pm7). outside the 1.5 clocks after a read out instruction, the current is C3 m a (max.). 4 . current which flows in the built-in pull-up or pull-down resistor is not included. remar k unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin. www.datasheet.net/ datasheet pdf - http://www..co.kr/
45 m pd78042f, 78043f, 78044f, 78045f dc characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol conditions min. typ. max. unit power supply i dd1 5.0 mhz crystal oscillation v dd = 5.0 v 10 % note 2 7.2 21.6 ma current note 1 operating mode v dd = 3.0 v 10 % note 3 0.9 2.7 ma i dd2 5.0 mhz crystal oscillation v dd = 5.0 v 10 % 1.3 3.9 ma halt mode v dd = 3.0 v 10 % 550 1650 m a i dd3 32.768 khz crystal oscillation v dd = 5.0 v 10 % 60 120 m a operating mode note 4 v dd = 3.0 v 10 % 35 70 m a i dd4 32.768 khz crystal oscillation v dd = 5.0 v 10 % 25 50 m a halt mode note 4 v dd = 3.0 v 10 % 5 10 m a i dd5 xt1 = 0 v v dd = 5.0 v 10 % 1 20 m a stop mode feedback resistor connected v dd = 3.0 v 10 % 0.5 10 m a i dd6 xt1 = 0 v v dd = 5.0 v 10 % 0.1 20 m a stop mode feedback resistor not connected v dd = 3.0 v 10 % 0.05 10 m a notes 1. this current excludes the av ref current, port current, and current which flows in the built-in pull-down resistor (mask option). 2. when operating at high-speed mode (when the processor clock control register (pcc) is set to 00h) 3. when operating at low-speed mode (when the pcc is set to 04h) 4. when the main system clock is stopped www.datasheet.net/ datasheet pdf - http://www..co.kr/
46 m pd78042f, 78043f, 78044f, 78045f operated with main system clock operated with subsystem clock v dd = 4.5 to 5.5 v v dd = 4.5 to 5.5 v intp0 intp1-intp3 t cy f ti t tih t til t inth t intl t rsl cycle time (minimum instruction execution time) ti1, 2 input frequency ti1, 2 input high, low-level width interrupt input high, low-level width reset low- level width conditions v dd = 4.5 to 5.5 v symbol parameter unit 0.4 0.8 40 note 1 0 0 250 3.6 8/f sam note 2 10 10 m s m s m s mhz khz ns m s m s m s m s 32 32 125 2 138 122 min. typ. max. ac characteristics (1) basic operation (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) notes 1. value when external clock input is used as subsystem clock. when crystal is used, the value becomes 114 m s. 2. selection of fsam = f x /2 n+1 , f x /64, f x /128 is available (n = 0 to 4) by bits 0 and 1 (scs0, scs1) of sampling clock select register (scs). t cy vs. v dd (with main system clock operated) 6 5 3 1 60 30 10 2.0 power supply voltage v dd [v] cycle time t cy [ s] 4 2 1.0 0.5 0.4 operation guarantee range 0 m www.datasheet.net/ datasheet pdf - http://www..co.kr/
47 m pd78042 f , 78043 f , 78044 f , 78045f (2 ) serial interface ( t a = C40 to +85 c, v d d = 2.7 to 5.5 v) (a ) serial interface channel 0 (i ) three-wire serial i/o mode (sck0: internal clock output) not e c is a load capacitance of the sck0 or so0 output line. (ii ) three-wire serial i/o mode (sck0: external clock input) not e c is a load capacitance of the so0 output line. parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy1 v dd = 4.5 to 5.5 v 800 n s 3200 n s sck0 high, low-level width t kh1 v dd = 4.5 to 5.5 v t kcy 1 /2 C 50 ns t kl1 t kcy 1 /2 C 150 ns si0 setup time to sck0 - t sik1 100 n s si0 hold time from sck 0 - t ksi1 400 n s sck 0 ?? so0 output t kso1 c = 100 pf note v dd = 4.5 to 5.5 v 300 n s delay time 1000 n s parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy2 v dd = 4.5 to 5.5 v 800 n s 3200 n s sck0 high, low-level width t kh2 v dd = 4.5 to 5.5 v 400 n s t kl2 1600 n s si0 setup time to sck0 - t sik2 v dd = 4.5 to 5.5 v 100 n s si0 hold time from sck 0 - t ksi2 400 n s sck 0 ? ? so0 output t kso2 c = 100 pf note v dd = 4.5 to 5.5 v 300 n s delay time 1000 n s sck0 rise time an d fall time t r2 160 n s t f2 www.datasheet.net/ datasheet pdf - http://www..co.kr/
48 m pd78042 f , 78043 f , 78044 f , 78045f (iii ) sbi mode (sck0: internal clock output) not e r is a load resistance of the sck0, sb0, or sb1 output line, and c is its load capacitance. (iv ) sbi mode (sck0: external clock input) not e r is a load resistance of the sb0 or sb1 output line, and c is its load capacitance. parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy3 v dd = 4.5 to 5.5 v 800 n s 3200 n s sck0 high, low-level width t kh3 v dd = 4.5 to 5.5 v t kcy 3 /2 C 50 ns t kl3 t kcy 3 /2 C 150 ns sb0, sb1 setup time to sck0 - t sik3 v dd = 4.5 to 5.5 v 100 n s 300 n s sb0, sb1 hold time from t ksi3 t kcy 3 /2 n s sck 0 - sck 0 ? ? sb0, sb1 output t kso3 r = 1 k w , v dd = 4.5 to 5.5 v 0 250 n s delay time c = 100 pf note 0 1000 n s sck 0 - ? sb0, sb 1 ? t ksb t kcy3 ns sb0, sb 1 ?? sck 0 ? t sbk t kcy3 ns sb0, sb1 high-level width t sbh t kcy3 ns sb0, sb1 low-level width t sbl t kcy3 ns parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy4 v dd = 4.5 to 5.5 v 800 n s 3200 n s sck0 high, low-level width t kh4 v dd = 4.5 to 5.5 v 400 n s t kl4 1600 n s sb0, sb1 setup time to sck0 - t sik4 v dd = 4.5 to 5.5 v 100 n s 300 n s sb0, sb1 hold time from t ksi4 t kcy 4 /2 n s sck 0 - sck 0 ? ? sb0, sb1 output t kso4 r = 1 k w , v dd = 4.5 to 5.5 v 0 300 n s delay time c = 100 pf note 0 1000 n s sck 0 - ? sb0, sb 1 ? t ksb t kcy4 ns sb0, sb 1 ? ? sck 0 ? t sbk t kcy4 ns sb0, sb1 high-level witdh t sbh t kcy4 ns sb0, sb1 low-level width t sbl t kcy4 ns sck0 rise time and fall time t r4 160 n s t f4 www.datasheet.net/ datasheet pdf - http://www..co.kr/
49 m pd78042 f , 78043 f , 78044 f , 78045f (v ) two-wire serial i/o mode (sck0: internal clock output) not e r is a load resistance of the sck0, sb0, or sb1 output line, and c is its load capacitance. (vi ) two-wire serial i/o mode (sck0: external clock input) not e r is a load resistance of the sb0 or sb1 output line, and c is its load capacitance. parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy5 r = 1 k w , v dd = 4.5 to 5.5 v 1600 n s c = 100 pf note 3800 n s sck0 high-level width t kh5 t kcy 5 /2 C 160 ns sck0 low-level width t kl5 t kcy 5 /2 C 50 ns sb0, sb1 setup time to sck0 - t sik5 300 n s sb0, sb1 hold time from t ksi5 600 n s sck 0 - sck 0 ?? sb0, sb1 output t kso5 v dd = 4.5 to 5.5 v 0 250 n s delay time 0 1000 n s parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy6 v dd = 4.5 to 5.5 v 1600 n s 3800 n s sck0 high-level width t kh6 650 n s sck0 low-level width t kl6 800 n s sb0, sb1 setup time to sck0 - t sik6 100 n s sb0, sb1 hold time from t ksi6 t kcy 6 /2 n s sck 0 - sck 0 ?? sb0, sb1 output t kso6 r = 1 k w , v dd = 4.5 to 5.5 v 0 300 n s delay time c = 100 pf note 0 1000 n s sck0 rise time and fall time t r6 160 n s t f6 www.datasheet.net/ datasheet pdf - http://www..co.kr/
50 m pd78042 f , 78043 f , 78044 f , 78045f (b ) serial interface channel 1 (i ) three-wire serial i/o mode (sck1: internal clock output) not e c is a load capacitance of the sck1 or so1 output line. (ii ) three-wire serial i/o mode (sck1: external clock input) not e c is a load capacitance of the so1 output line. parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy7 v dd = 4.5 to 5.5 v 800 n s 3200 n s sck1 high, low-level width t kh7 v dd = 4.5 to 5.5 v t kcy 7 /2 C 50 ns t kl7 t kcy 7 / 2 C 150 ns si1 setup time to sck1 - t sik7 100 n s si1 hold time from sck 1 - t ksi7 400 n s sck 1 ?? so1 output delay t kso7 c = 100 pf note v dd = 4.5 to 5.5 v 300 n s time 1000 n s parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy8 v dd = 4.5 to 5.5 v 800 n s 3200 n s sck1 high, low-level width t kh8 v dd = 4.5 to 5.5 v 400 n s t kl8 1600 n s si1 setup time to sck1 - t sik8 v dd = 4.5 to 5.5 v 100 n s si1 hold time from sck 1 - t ksi8 400 n s sck 1 ? ? so1 output delay t kso8 c = 100 pf note v dd = 4.5 to 5.5 v 300 n s time 1000 n s sck1 rise time an d fall time t r8 160 n s t f8 www.datasheet.net/ datasheet pdf - http://www..co.kr/
51 m pd78042 f , 78043 f , 78044 f , 78045f (iii ) 3-wire serial i/o mode with automatic transmission/reception function (sck1: internal clock output) not e c is a load capacitance of the sck1 or so1 output line. (iv ) 3-wire serial i/o mode with automatic transmission/reception function (sck1: external clock input) not e c is a load capacitance of the so1 output line. parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy9 v dd = 4.5 to 5.5 v 800 n s 3200 n s sck1 high, low-level width t kh9 v dd = 4.5 to 5.5 v t kcy 9 /2 C 50 ns t kl9 t kcy 9 / 2 C 150 ns si1 setup time to sck1 - t sik9 100 n s si1 hold time from sck 1 - t ksi9 400 n s sck 1 ? ? so1 output delay time t kso9 c = 100 pf note v dd = 4.5 to 5.5 v 300 n s 1000 n s sck 1 - ? st b ? t sbd t kcy 9 / 2 C 100 t kcy 9 /2 + 100 ns strobe signal high level width t sbw t kcy9 C 30 t kcy9 + 30 ns busy signal setup time (to bus y t bys 100 n s signal detection timing) busy signal hold time (to busy t byh 100 n s signal detection timing) busy inactiv e ? sck 1 ? t sps 2t kcy9 ns parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy10 v dd = 4.5 to 5.5 v 800 n s 3200 n s sck1 high, low-level width t kh10 v dd = 4.5 to 5.5 v 400 n s t kl10 1600 n s si1 setup time to sck 1 - t sik10 100 n s si1 hold time from sck 1 - t ksi10 400 n s sck 1 ?? so1 output delay t kso10 c = 100 pf note v dd = 4.5 to 5.5 v 300 n s time 1000 n s sck1 rise time and fall time t r10 160 n s t f10 www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 52 ac timing test points (except x1, xt1 input) clock timing ti timing 0.8v dd 0.2v dd 0.8v dd 0.2v dd test points ti1, ti2 1/f ti t til t tih xt1 input v dd ?0.5 v 0.4 v 1/f xt t xtl t xth 1/f x t xl t xh v dd ?0.5 v 0.4 v x1 input www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 53 sb0, sb1 sck0 t ksb t sbk t kcy3, 4 t kl3, 4 t kh3, 4 t kso3, 4 t sik3, 4 t ksi3, 4 serial transfer timing 3-wire serial i/o mode: sbi mode (bus release signal transfer): sbi mode (command signal transfer): t kcy1, 2, 7, 8 t kl1, 2, 7, 8 t kh1, 2, 7, 8 t sik1, 2, 7, 8 t ksi1, 2, 7, 8 input data t kso1, 2, 7, 8 output data so0, so1 si0, si1 sck0, sck1 t r2, 8 t f2, 8 t kl3, 4 t kcy3, 4 sb0, sb1 sck0 t ksb t sbl t sbh t sbk t kh3, 4 t sik3, 4 t ksi3, 4 t kso3, 4 t r4 t f4 www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 54 t kcy5, 6 sck0 t kl5, 6 t kh5, 6 t sik5, 6 t ksi5, 6 t kso5, 6 sb0, sb1 t r6 t f6 2-wire serial i/o mode: 3-wire serial i/o mode with automatic transmission/reception function: 3-wire serial i/o mode with automatic transmission/reception function (busy processing): note sck does not become low actually at this point, but is indicated so to conform to the timing specification. t sik9, 10 t kso9, 10 t ksi9, 10 t kh9, 10 t f10 t r10 t kl9, 10 t kcy9, 10 t sbd t sbw so1 si1 sck1 stb d2 d0 d1 d2 d0 d1 d7 d7 789 note 10 note 10 + n note 1 sck1 busy (active high) t bys t byh t sps www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042 f , 78043 f , 78044 f , 78045f 55 a/d c onverter characteristics ( t a = C40 to +85 c, av dd = v dd = 4.0 to 5.5 v, a v s s = v s s = 0 v) note s 1 . quantization error (1/2lsb) is not included. this parameter is indicated as the ratio to the full-scale value. 2 . set the a/d conversion time to 19.1 m s or more. 3 . sampling time depends on the conversion time. parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit total error note 1 0.8 % conversion time note 2 t conv 1 mhz - f x - 5.0 mhz 19.1 200 m s sampling time note 3 t samp 2.86 3 0 m s analog signal input v ian a v ss a v ref v voltage reference voltage av ref 4.0 av dd v a v ref resistor r avref 4 1 4 k w a v dd current ai dd 200 400 m a www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 56 data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85 c) note selection of 2 12 /f x , 2 14 /f x to 2 17 /f x is available by bits 0 to 2 (osts0 to osts2) of oscillation settling time select register (osts). data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal) parameter symbol conditions min. typ. max. unit data retention supply v dddr 2.0 5.5 v voltage data retention supply i dddr v dddr = 2.0 v 0.1 10 m a current subsystem clock stopped feedback resistor not connected release signal set time t srel 0 m s oscillation stabilization t wait release by reset 2 17 /f x ms wait time release by interrupt note ms stop mode data retention mode t wait operating mode halt mode internal reset operation stop instruction execution v dddr v dd reset t srel stop mode data retention mode t wait operating mode halt mode stop instruction execution v dddr v dd standby release signal (interrupt request) t srel www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 57 interrupt input timing reset input timing t intl intp0-intp2 t inth t intl intp3 reset t rsl www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 58 11. characteristic curve (reference value) h pcc = 00h pcc = 01h pcc = 02h pcc = 03h pcc = 04h pcc = 30h halt (x1 and xt1 oscillate) f x = 5.0 mhz f xt = 32.768 khz pcc = b0h halt (x1 stops but xt1 oscillates) (x1 stops but xt1 oscillates) stop 10.0 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 0234 supply voltage v dd [v] supply current i dd [ma] 5678 (t a = 25 ?) i dd vs. v dd (main system clock: 5.0 mhz) www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 59 0 0 4 3 2 1 6 5 4 3 2 1 pcc = 00h pcc = 01h pcc = 02h pcc = 03h pcc = 04h halt (x1 oscil- lates) clock oscillation frequency f x [mhz] supply current i dd [ma] i dd vs. f x (v dd = 3 v, t a = 25 ?) 0 0 4 5 7 6 3 2 1 6 5 4 3 2 1 pcc = 00h pcc = 01h pcc = 02h pcc = 03h pcc = 04h halt (x1 oscil- lates) clock oscillation frequency f x [mhz] supply current i dd [ma] i dd vs. f x (v dd = 5 v, t a = 25 ?) www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 60 30 20 10 0 0 0.5 1.0 1.5 v ol vs. i ol (port 1) v dd = 6 v v dd = 5 v v dd = 3 v v dd = 4 v low-level output voltage v ol [v] low-level output currnt i ol [ma] (t a = 25 ?) 30 20 10 0 0 0.5 1.0 1.5 (t a = 25 ?) v ol vs. i ol (ports 0, 2, and 3) low-level output voltage v ol [v] low-level output current i ol [ma] v dd = 6 v v dd = 3 v v dd = 5 v v dd = 4 v www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 61 30 20 10 0 0 0.5 1.0 1.5 v dd = 6 v v dd = 5 v v dd = 4 v v dd = 3 v (t a = 25 ?) v ol vs. i ol (port 7) low-level output voltage v ol [v] low-level output current i ol [ma] www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 62 ?0 ?0 ?0 0 0 1.0 2.0 3.0 (t a = 25 ?) v dd ?v oh vs. i oh (port 8 - port 12) high-level output voltage v dd ?v oh [v] high-level output current i oh [ma] v dd = 3 v v dd = 6 v v dd = 5 v v dd = 4 v ?0 ? 0 0 0.5 1.0 1.5 (t a = 25 ?) v dd ?v oh vs. i oh (port 0 - port 3) high-level output voltage v dd ?v oh [v] high-level output current i oh [ma] v dd = 5 v v dd = 6 v v dd = 4 v v dd = 3 v www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 63 12. package drawing remark the shape and material of the es version are the same as those of the corresponding mass-produced product. h 80 pin plastic qfp (14 20) note each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. detail of lead end m f g h i j k m l n p q r item millimeters inches s p80gf-80-3b9-3 3.0 max. 0.119 max. k 1.8?.2 0.071 +0.008 ?.009 l 0.8?.2 0.031 +0.009 ?.008 p 2.7 0.106 n 0.10 0.004 m 0.15 0.006 +0.004 ?.003 q 0.1?.1 0.004?.004 a 23.6?.4 0.929?.016 b 20.0?.2 0.795 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 g f 0.8 1.0 0.031 0.039 d 17.6?.4 0.693?.016 j 0.8 (t.p.) 0.031 (t.p.) i 0.15 0.006 h 0.35?.10 0.014 +0.004 ?.005 +0.10 ?.05 64 65 40 80 1 25 24 41 a b cd s r5 ? 5 ? www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 64 h 13. recommended soldering conditions the conditions listed below shall be met when soldering the m pd78042f, m pD78043F, m pd780 44f, or m pd78045f. for details of the recommended soldering conditions, refer to our document semiconductor device mounting technology manual (c10535e). please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. table 13-1 soldering conditions for surface-mount devices m m m m m pd78042fgf- -3b9: 80-pin plastic qfp (14 20 mm) m m m m m pD78043Fgf- -3b9: 80-pin plastic qfp (14 20 mm) m m m m m pd78044fgf- -3b9: 80-pin plastic qfp (14 20 mm) m m m m m pd78045fgf- -3b9: 80-pin plastic qfp (14 20 mm) caution do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections). soldering process soldering conditions recommended conditions infrared ray reflow peak package's surface temperature: 235 c ir35-00-3 reflow time: 30 seconds or less (210 c or more) maximum allowable number of reflow processes: 3 vps peak package's surface temperature: 215 c vp15-00-3 reflow time: 40 seconds or less (200 c or more) maximum allowable number of reflow processes: 3 wave soldering solder temperature: 260 c or less ws60-00-1 flow time: 10 seconds or less number of flow processes: 1 preheating temperature : 120 c max. (measured on the package surface) partial heating method terminal temperature: 300 c or less heat time: 3 seconds or less (for one side of a device) www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 65 appendix a development tools the following tools are available for development of systems using the m pd78042f, m pD78043F, m pd78044f, or m pd78045f. language processing software ra78k/0 notes 1, 2, 3, 4 assembler package common to 78k/0 series cc78k/0 notes 1, 2, 3, 4 c compiler package common to 78k/0 series df78044 notes 1, 2, 3, 4 device file for m pd78044a subseries cc78k/0-l notes 1, 2, 3, 4 c compiler library source file common to 78k/0 series prom writing tools pg-1500 prom programmer pa-78p048gf programmer adapter connected to pg-1500 pa-78p048kl-s pg-1500 controller notes 1, 2 control program for pg-1500 debugging tools ie-78000-r in-circuit emulator common to 78k/0 series ie-78000-r-a note 8 in-circuit emulator common to 78k/0 series (for integrated debugger) ie-78000-r-bk break board common to 78k/0 series ie-78044-r-em emulation board for evaluating m pd78044a subseries ep-78130gf-r emulation probe common to m pd78134 ev-9200g-80 socket mounted on target system created for 80-pin plastic qfp sm78k0 notes 5, 6, 7 system simulator common to 78k/0 series id78k0 notes 4, 5, 6, 7, 8 integrated debugger for ie-78000-r-a sd78k/0 notes 1, 2 screen debugger for ie-78000-r df78044 notes 1, 2, 5, 6, 7 device file common to m pd78044a subseries real-time os rx78k/0 notes 1, 2, 3, 4 real-time os for 78k/0 series mx78k0 notes 1, 2, 3, 4 os for 78k/0 series notes 1. pc-9800 series (ms-dos tm ) based 2. ibm pc/at tm and compatible (pc dos tm /ibm dos tm /ms-dos) based 3. hp9000 series 300 tm (hp-ux tm ) based 4. hp9000 series 700 tm (hp-ux) based, sparcstation tm (sunos tm ) based, ews-4800 series (ews- ux/v) based 5. pc-9800 series (ms-dos + windows tm ) based 6. ibm pc/at and compatible (pc dos/ibm dos/ms-dos + windows) based 7. news tm (news-os tm ) based 8. under development h h h www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 66 fuzzy inference development support system fe9000 note 1 /fe9200 note 3 fuzzy knowledge data creation tool ft9080 note 1 /ft9085 note 2 translator fi78k0 notes 1, 2 fuzzy inference module fd78k0 notes 1, 2 fuzzy inference debugger notes 1. pc-9800 series (ms-dos) based 2. ibm pc/at and compatible (pc dos/ibm dos/ms-dos) based 3. ibm pc/at and compatible (pc dos/ibm dos/ms-dos + windows) based remarks 1. please refer to the 78k/0 series selection guide (u11126e) for information on third party develop- ment tools. 2. ra78k/0, cc78k/0, sm78k/0, id78k0, sd78k/0, and rx78k/0 are used in combination with df78044. www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 67 appendix b related documents ? documents related to devices document name document no. japanese english m pd78044f sub-series users manual u10908j u10908e m pd78042f, 78043f, 78044f, 78045f data sheet u10700j this manual m pd78p048a data sheet u10611j u10611e m pd78044a, 78044f sub-series special function registers u10701j 78k/0 series users manual, instruction ieu-849 ieu-1372 78k/0 series instruction summary sheet u10903j 78k/0 series instruction set u10904j ? documents related to development tools (users manual) document name document no. japanese english ra78k series assembler package operation eeu-809 eeu-1399 language eeu-815 eeu-1404 ra78k series structured assembler preprocessor eeu-817 eeu-1402 cc78k series c compiler operation eeu-656 eeu-1280 language eeu-655 eeu-1284 cc78k/0 compiler application note programming know-how eea-618 eea-1208 cc78k series library source file eeu-777 pg-1500 prom programmer eeu-651 eeu-1335 pg-1500 controller pc-9800 series (ms-dos) base eeu-704 eeu-1291 pg-1500 controller ibm pc series (pc dos) base eeu-5008 u10540e ie-78000-r eeu-810 u11376e ie-78000-r-a u10057j u10057e ie-78000-r-bk eeu-867 eeu-1427 ie-78044-r-em eeu-833 eeu-1424 ep-78130gf-r eeu-943 eeu-1470 sm78k0 system simulator reference eeu-5002 u10181e sm78k series system simulator external parts user open u10092j u10092e interface specifications id78k0 integrated debugger reference u11151j sd78k/0 screen debugger tutorial eeu-852 u10539e pc-9800 series (ms-dos) base reference eeu-816 sd78k/0 screen debugger tutorial eeu-5024 eeu-1414 ibm pc/at (pc dos) base reference u11279j eeu-1413 caution the above documents may be revised without notice. use the latest versions when you design an application system. h h www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 68 ? documents related to software to be incorporated into the product (users manual) document name document no. japanese english 78k/0 series real-time os basic eeu-912 installation eeu-911 technical eeu-913 os for 78k/0 series mx78k0 basic eeu-5010 tool for creating fuzzy knowledge data eeu-829 eeu-1438 78k/0, 78k/ii, and 87ad series fuzzy inference development eeu-829 eeu-1444 support system, translator 78k/0 series fuzzy inference development support system, eeu-858 eeu-1441 fuzzy inference module 78k/0 series fuzzy inference development support system, eeu-921 eeu-1458 fuzzy inference debugger ? other documents document name document no. japanese english ic package manual c10943x smd surface mount technology manual c10535j c10535e quality grades on nec semiconductor device iei-620 iei-1209 nec semiconductor device reliability/quality control system c10983j c10983e electrostatic discharge (esd) test mem-539 guide to quality assurance for semiconductor device mei-603 mei-1202 guide for products related to micro-computer: other companies mei-604 caution the above documents may be revised without notice. use the latest versions when you design an application system. h www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 69 [memo] www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 70 cautions on cmos devices countermeasures against static electricity for all moss caution when handling mos devices, take care so that they are not electrostatically charged. strong static electricity may cause dielectric breakdown in gates. when transporting or storing mos devices, use conductive trays, magazine cases, shock absorbers, or metal cases that nec uses for packaging and shipping. be sure to ground mos devices during assembling. do not allow mos devices to stand on plastic plates or do not touch pins. also handle boards on which mos devices are mounted in the same way. cmos-specific handling of unused input pins caution hold cmos devices at a fixed input level. unlike bipolar or nmos devices, if a cmos device is operated with no input, an intermediate- level input may be caused by noise. this allows current to flow in the cmos device, resulting in a malfunction. use a pull-up or pull-down resistor to hold a fixed input level. since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the v dd or gnd pin through a resistor. if handling of unused pins is documented, follow the instructions in the document. statuses of all mos devices at initialization caution the initial status of a mos device is unpredictable when power is turned on. since characteristics of a mos device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. nec has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. however, nec assures operation after reset and items for mode setting if they are defined. when you turn on a device having a reset function, be sure to reset the device first. fip is a trademark of nec corporation. iebus is trademark of nec corporation. ms-dos and windows are trademarks of microsoft corporation. ibm dos, pc/at, and pc dos are trademarks of ibm corporation. hp9000 series 300, hp9000 series 700, and hp-ux are trademarks of hewlett-packard. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation. www.datasheet.net/ datasheet pdf - http://www..co.kr/
m pd78042f, 78043f, 78044f, 78045f 71 nec electronics inc. (u.s.) mountain view, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby sweden tel: 8-63 80 820 fax: 8-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 3 www.datasheet.net/ datasheet pdf - http://www..co.kr/
72 m pd78042f, 78043f, 78044f, 78045f note that preliminary is not indicated in this document, even though the related documents may be preliminary versions. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 94. 11 www.datasheet.net/ datasheet pdf - http://www..co.kr/

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